Optical networks continue to evolve with greater performance and flexibility based on a foundation of CMOS chip designs as the latest designs are heading to market in 2019. The next-generation of coherent chip designs will segment into two different paths, one targeting high performance and flexibility, and the other targeting low power and area. New semiconductor design techniques, both to advance performance in spectral efficiency and circuit optimization for power efficiency, pave the way for these upcoming new generations of coherent DSP chips. The path forward for future generations of coherent chip designs with respect to CMOS process technology must be carefully considered.
White Paper
High-performance Coherent in CMOS: Foundational Technology for WDM Optical Networking
Related
View more insightsBlog
Delivering on the promise of CPO/NPO at hyperscale with Vesta 200 6.4T CPX light engine
Cloud service providers are clear about what they need from AI networking: scale, density, reliability, low power, and cost efficiency. Discover how the Ciena Vesta 200 6.4T optical engine was architected to deliver the right balance across all five
ReadBlog
How open ecosystems will advance CPO adoption
As AI infrastructure scales, the limitations of pluggable optics in the data center are becoming increasingly apparent. Ciena’s Matt Bolig explains how this shift is setting the stage for co-packaged optics to redefine how bandwidth is delivered
ReadVideos
Fierce Network: Scaling AI with Next-Gen Optical Networks
Ciena’s Mark Bieberich discusses AI-driven demand, optical network expansion, high-performance optics, coherent solutions, and scaling capacity for hyperscalers.
Watch